rfics-presentation/sections/03_simulation_results.tex

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\section{Own Simulations}
\label{sec:Own Simulation}
\begin{frame}
\frametitle{Design Steps}
\begin{enumerate}
\item Determination of operating point of individual stages
\begin{itemize}
\item SQuad
\item TIA
\item Buffer
\end{itemize}
\item Integration
\begin{itemize}
\item SQuad \& TIA
\item SQuad, TIA \& Buffer
\end{itemize}
\item Matching of input and output
\item Replacement of remaining DC blocks/feeds in bias circuitry
\item Final optimization
\end{enumerate}
\end{frame}
\begin{frame}
\frametitle{Operating Point: Switching Quad}
\begin{minipage}{0.5\textwidth}
\begin{itemize}
\item Operation
\begin{itemize}
\item Responsible for actual mixing
\item Multiplication of RF-signal with square wave $\rightarrow$ generation of mixing products at IF-frequency and harmonics
\end{itemize}
\end{itemize}
\bigskip
\begin{itemize}
\item Determination of operating point
\begin{itemize}
\item Exact value of $V_\text{CE}$ not crucial
\item $V_\text{BE}$: Examination of $s_\text{21}$
of Large-signal s-parameter simulation and noise figure (analogous to \citereference{Mai+21})
\item [TODO] (Simulate noise figure or remove text)
\end{itemize}
\end{itemize}
\end{minipage}%
\begin{minipage}{0.5\textwidth}
\centering
\begin{figure}[H]
\vspace*{-5mm}
\hspace*{15mm}%
\includegraphics[width=0.83\textwidth]{res/simulation/SQuad_OP_01.pdf}
\vspace*{-18mm}
\hspace*{-55mm}%
\includegraphics[width=0.4\textwidth]{res/simulation/SQuad_OP_02.pdf}
\end{figure}
\end{minipage}
\vspace{4mm}
\addreference{Mai+21}{T. Maiwald et al., ``A Broadband Zero-IF Down-Conversion Mixer in 130 nm SiGe BiCMOS for Beyond 5G Communication Systems in D-Band'', in \emph{IEEE Transactions on Circuits and Systems II: Express Briefs}, vol. 68, no. 7, pp. 2277-2281, July 2021}
\end{frame}
\begin{frame}
\frametitle{Operating Point: Transimpedance Amplifier}
\begin{minipage}{0.5\textwidth}
\begin{itemize}
\item Operation
\begin{itemize}
\item Conversion of switched current to voltage, amplification
\item Modified Cherry-Hooper topology: decoupling of bandwidth and gain, modification for greater dynamic range
\end{itemize}
\end{itemize}
\bigskip
\begin{itemize}
\item Determination of operating point
\begin{itemize}
\item Exact value of supply voltage not crucial
\item S-parameter simulation: Examination of maximum available gain ($\mathit{MAG}$) and minimum noise figure ($\mathit{NF}_\text{min}$)
\end{itemize}
\end{itemize}
\end{minipage}%
\begin{minipage}{0.5\textwidth}
\vspace*{-6mm}
\begin{figure}[H]
\centering
\hspace*{-8mm}
\includegraphics[width=0.83\textwidth]{res/simulation/TIA_OP_01.pdf}
\vspace*{-20mm}
\hspace*{58mm}%
\includegraphics[width=0.33\textwidth]{res/simulation/TIA_OP_02.pdf}
\end{figure}
\end{minipage}
\end{frame}
\begin{frame}
\frametitle{Operating Point: Buffer}
\begin{minipage}{0.45\textwidth}
\begin{itemize}
\item Operation
\begin{itemize}
\item Amplification of signal
\item Comprises three stages: two differential amplifiers and an emitter follower
\end{itemize}
\end{itemize}
\bigskip
\begin{itemize}
\item Determination of operating point
\begin{itemize}
\item Exact value of supply voltage not crucial at this point
\item S-parameter simulation: Examination of $\mathit{MAG}$ and $\mathit{NF}_\text{min}$
\item \textbf{Note}: Adjustment with respect to linearity at the very end
\item [TODO] Switch figure with correct one (add peaking inductance)
\end{itemize}
\end{itemize}
\end{minipage}%
\begin{minipage}{0.57\textwidth}
\vspace*{-5mm}
\begin{figure}[H]
\hspace*{2mm}%
\includegraphics[width=1\textwidth]{res/simulation/Buffer.pdf}
\end{figure}
\end{minipage}
\end{frame}
\begin{frame}
\frametitle{Integration: SQuad \& TIA}
\begin{minipage}{0.45\textwidth}
\begin{itemize}
\item DC coupling $\rightarrow$ Redesign of bias circuitry
\item Supply voltage fixed to $\SI{2.5}{\volt}$ to not exceed breakdown voltage of transistors
\item Examination using Harmonic-Balance simulation:
\begin{itemize}
\item Conversion gain
\item $\SI{1}{dB}$ compression point ($P_{\SI{1}{dB}}$)
\item[TODO] Noise figure
\end{itemize}
\end{itemize}
\end{minipage}%
\begin{minipage}{0.6\textwidth}
\vspace*{-38mm}
\begin{figure}[H]
\includegraphics[width=0.67\textwidth]{res/simulation/INT_SQuad_TIA_01.pdf}
\vspace*{-50mm}
\hspace{-70mm}%
\includegraphics[width=0.28\textwidth]{res/simulation/INT_SQuad_TIA_02.pdf}
\vspace*{-20mm}
\hspace{60mm}%
\includegraphics[width=0.22\textwidth]{res/simulation/INT_SQuad_TIA_03.pdf}
\end{figure}
\end{minipage}
\end{frame}
\begin{frame}
\frametitle{Integration: SQuad, TIA \& Buffer}
\begin{itemize}
\item AC coupling $\rightarrow$ No redesign of bias circuitry required
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{Further Optimization: \ldots}
\end{frame}
%\begin{frame}
% \frametitle{Simulation Setup}
%
% \begin{figure}[H]
% \centering
%
% \includegraphics[width=0.6\textwidth]{res/simulation/schematic.pdf}
% \end{figure}
%
% \begin{itemize}
% \item [TODO] Simulation schematics
% \item [TODO] Differences to schematic from paper (if any)
% \end{itemize}
%\end{frame}
%
%\begin{frame}
% \frametitle{Design Steps}
%
% \begin{itemize}
% \item [TODO] Idea: approach from lecture: first worry about actual circuit, biasing later
% \item [TODO] Choice of transistors
% \item [TODO] Choice of operating points
% \item [TODO] Rest of schematic details (?)
% \end{itemize}
%\end{frame}
%
%\begin{frame}
% \frametitle{Simulation Results}
%
% \begin{itemize}
% \item [TODO] Simulation results
% \item [TODO] Intuitive explanation of results
% \end{itemize}
%\end{frame}
%
%\begin{frame}
% \frametitle{Comparison with Standard Topology}
%
% \begin{itemize}
% \item [TODO] (Remove if not applicable)
% \item [TODO] Comparison of pros and cons of each topology
% \item [TODO] Comparison of simulation results
% \end{itemize}
%\end{frame}