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Finished first complete version

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Andreas Tsouchlos
2024-09-10 01:49:09 +02:00
parent a7b4ad0632
commit be38796b99
12 changed files with 419 additions and 29 deletions
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112
sections/03_simulation_results.tex
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@@ -19,7 +19,6 @@
\end{itemize}
\item Further iterative optimization of parameters (e.g., determine LO power,\\ increase buffer current for linearity, \ldots)
\item Matching of input and output
\item Replacement of remaining DC blocks/feeds in bias circuitry
\end{enumerate}
\end{frame}
@@ -438,7 +437,7 @@
\end{tikzpicture}
\end{subfigure}%
\begin{subfigure}{0.5\textwidth}
\hspace{2mm}
\hspace{2mm}
\begin{tikzpicture}
\begin{axis}[
width=\textwidth,
@@ -459,7 +458,7 @@
\end{subfigure}%
\begin{subfigure}{0.5\textwidth}
\hspace{1.5mm}
\hspace{1.5mm}
\begin{tikzpicture}
\begin{axis}[
width=\textwidth,
@@ -491,8 +490,6 @@
\addplot+[mark=none, line width=1pt]
table[col sep=comma, x=f, y=NF]
{res/simulation/INT_Buffer_noise.csv};
\draw[dashed] (axis cs:135, 0) -- (axis cs:135,12);
\node at (axis cs:147,1.25) {$f_\text{LO} = \SI{135}{GHz}$};
\end{axis}
\end{tikzpicture}
\end{subfigure}%
@@ -502,18 +499,109 @@
\begin{frame}
\frametitle{Final Circuit}
\begin{itemize}
\item [TODO] A few key points
\item [TODO] Circuit diagram
\end{itemize}
\begin{figure}[H]
\centering
\vspace*{-20mm}
\hspace{40mm}
\includegraphics[width=0.7\textwidth]{res/simulation/final_01.pdf}
\vspace*{-40mm}
\hspace{-120mm}
\includegraphics[width=0.2\textwidth]{res/simulation/final_02.pdf}
\end{figure}
\end{frame}
\begin{frame}
\frametitle{Final Circuit}
\begin{itemize}
\item [TODO] 4 Plots of same stuff as in paper
\end{itemize}
\vspace*{-6mm}
\begin{figure}
\begin{subfigure}{0.5\textwidth}
\begin{tikzpicture}
\begin{axis}[
width=\textwidth,
height=0.5\textwidth,
ylabel={$20 \log_{10}(s_{xy})$ (dB)},
xlabel={$f (\text{GHz})$},
legend pos = south east,
grid,
]
\addplot+[mark=none, line width=1pt]
table[col sep=comma, x=f, y=SRF]
{res/simulation/final_S_RF.csv};
\addlegendentry{$s_{11}$ (RF)}
\addplot+[mark=none, line width=1pt]
table[col sep=comma, x=f, y=SLO]
{res/simulation/final_S_LO.csv};
\addlegendentry{$s_{22}$ (LO)}
\end{axis}
\end{tikzpicture}
\end{subfigure}%
\begin{subfigure}{0.5\textwidth}
\hspace{2mm}
\begin{tikzpicture}
\begin{axis}[
width=\textwidth,
height=0.5\textwidth,
ylabel={Conversion Gain (dB)},
xlabel={$f_\text{RF}\ (\text{GHz})$},
xtick={-110,-100,...,170},
ytick={10,15,...,40},
grid,
]
\addplot+[mark=none, line width=1pt]
table[col sep=comma, x=RFFreq, y=ConvGain]
{res/simulation/final_ConvGain_vs_RFFreq.csv};
\draw[dashed] (axis cs:135, 5) -- (axis cs:135,40);
\node at (axis cs:147,12) {$f_\text{LO} = \SI{135}{GHz}$};
\end{axis}
\end{tikzpicture}
\end{subfigure}%
\begin{subfigure}{0.5\textwidth}
\begin{tikzpicture}
\begin{axis}[
width=\textwidth,
height=0.5\textwidth,
ylabel={$\mathit{NF}_\text{dsb}\ (\text{dB})$},
xlabel={$f_\text{IF}\ (\text{GHz})$},
xtick={0,5,...,30},
ytick={9,9.5,...,11.5},
grid,
]
\addplot+[mark=none, line width=1pt]
table[col sep=comma, x=f, y=NF]
{res/simulation/final_noise.csv};
\end{axis}
\end{tikzpicture}
\end{subfigure}%
\begin{subfigure}{0.5\textwidth}
\begin{tikzpicture}
\begin{axis}[
width=\textwidth,
height=0.5\textwidth,
ylabel={Conversion Gain (dB)},
xlabel={$P_\text{RF} / P_\text{LO} \ (\text{dBm})$},
legend pos = south west,
xtick = {-90,-80,...,10},
ytick = {-60,-40,...,40},
grid,
]
\addplot+[mark=none, line width=1pt]
table[col sep=comma, x=RFPow, y=ConvGain]
{res/simulation/final_ConvGain_vs_RFPow.csv};
\addlegendentry{RF}
\addplot+[mark=none, line width=1pt]
table[col sep=comma, x=LOPow, y=ConvGain]
{res/simulation/final_ConvGain_vs_LOPow.csv};
\addlegendentry{LO}
\end{axis}
\end{tikzpicture}
\end{subfigure}%
\end{figure}
\end{frame}
%\begin{frame}

18
sections/05_conclusion.tex
View File

@@ -5,24 +5,22 @@
\frametitle{Discussion \& Conclusion}
\begin{itemize}
\item Mixer structure
\item General structure
\begin{itemize}
\item Removal of $g_\text{m}$ stage of Gilbert cell $\rightarrow$ more voltage headroom
\item High bandwidth TIA and inductive peaking $\rightarrow$ high bandwidth
\item Differential to single-ended conversion $\rightarrow$ dense chip-to-package transition
\end{itemize}
\bigskip
\item Own simulations
\begin{itemize}
\item Much higher conversion gain $\leftarrow$ technology with higher $f_\text{t}$ and $f_\text{max}$, no stability considerations
\end{itemize}
\bigskip
% \item Own simulations
% \begin{itemize}
% \item Much higher conversion gain $\leftarrow$ technology with higher $f_\text{t}$ and $f_\text{max}$, no stability considerations
% \end{itemize}
% \bigskip
\item Applications of this design
\begin{itemize}
\item [TODO] Applications of proposed design (why specifically 5G?)
\begin{itemize}
\item [TODO] Are BiCMOS devices, e.g., particularly cheap or easily scalable?
\end{itemize}
\item SiGe HBT technology integrable with CMOS $\rightarrow$ scalable, suitable for mixed-signal ICs
\item Ideal for electronic beam stearing in mm-Wave applications
\end{itemize}
\end{itemize}
\end{frame}