From 0aa778c8a1c2d2e5231ec9496ca898fd47b4d112 Mon Sep 17 00:00:00 2001 From: Andreas Tsouchlos Date: Tue, 10 Sep 2024 05:22:46 +0200 Subject: [PATCH] Final edits --- sections/02_proposed_ideas.tex | 4 ++-- sections/03_simulation_results.tex | 16 +++++++++------- sections/05_conclusion.tex | 14 ++++++-------- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/sections/02_proposed_ideas.tex b/sections/02_proposed_ideas.tex index 30e1c4c..930966e 100644 --- a/sections/02_proposed_ideas.tex +++ b/sections/02_proposed_ideas.tex @@ -71,9 +71,9 @@ \vspace*{1mm} \begin{itemize} - \item High bandwidth, low power consumption, small size + \item High bandwidth, low noise figure, low power consumption, small size \item Applicable to electronic beam stearing for mm-Wave - \item SiGe BiCMOS technology (B11HFC) from Infineon Technologies AG with $f_\text{t}/f_\text{max}$ of $250/\SI{370}{\giga\hertz}$ + \item 130nm SiGe BiCMOS technology from Infineon Technologies AG with $f_\text{t}/f_\text{max}$ of $250/\SI{370}{\giga\hertz}$ \end{itemize} \vspace*{2mm} diff --git a/sections/03_simulation_results.tex b/sections/03_simulation_results.tex index d58d842..49306ca 100644 --- a/sections/03_simulation_results.tex +++ b/sections/03_simulation_results.tex @@ -18,7 +18,7 @@ \item SQuad, TIA \& Buffer \end{itemize} \item Further iterative optimization of parameters (e.g., determine LO power,\\ increase buffer current for linearity, \ldots) - \item Matching of input and output + \item Matching \end{enumerate} \end{frame} @@ -288,6 +288,7 @@ \begin{itemize} \item Conversion gain \item $\SI{1}{dB}$ compression point ($P_{\SI{1}{dB}}$) + \item Noise figure \end{itemize} \end{itemize} \end{minipage}% @@ -402,6 +403,7 @@ \begin{itemize} \item Conversion gain \item $\SI{1}{dB}$ compression point ($P_{\SI{1}{dB}}$) + \item Noise figure \end{itemize} \end{itemize} \end{minipage}% @@ -523,7 +525,7 @@ ylabel={$20 \log_{10}(s_{xy})$ (dB)}, xlabel={$f (\text{GHz})$}, legend pos = south east, - grid, + grid, ] \addplot+[mark=none, line width=1pt] @@ -583,20 +585,20 @@ height=0.5\textwidth, ylabel={$P_\text{IF}\ (\text{dBm})$}, xlabel={$P_\text{RF} / P_\text{LO} \ (\text{dBm})$}, - legend pos = south west, - xtick = {-90,-80,...,10}, - ytick = {-100,-80,...,0}, + legend pos = south west, + xtick = {-90,-80,...,10}, + ytick = {-100,-80,...,0}, grid, ] \addplot+[mark=none, line width=1pt] table[col sep=comma, x=RFPow, y expr=(\thisrowno{1}-40)] {res/simulation/final_ConvGain_vs_RFPow.csv}; - \addlegendentry{RF} + \addlegendentry{RF} \addplot+[mark=none, line width=1pt] table[col sep=comma, x=LOPow, y expr=(\thisrowno{1}-40)] {res/simulation/final_ConvGain_vs_LOPow.csv}; - \addlegendentry{LO} + \addlegendentry{LO} \end{axis} \end{tikzpicture} \end{subfigure}% diff --git a/sections/05_conclusion.tex b/sections/05_conclusion.tex index c920a99..327e399 100644 --- a/sections/05_conclusion.tex +++ b/sections/05_conclusion.tex @@ -5,6 +5,12 @@ \frametitle{Discussion \& Conclusion} \begin{itemize} + \item Own simulations + \begin{itemize} + \item Better results to be expected (technology with higher $f_\text{t}$, $f_\text{max}$, stability not considered) + \item Maybe better results by using current mirrors to set operating points of buffer instead of resistors + \end{itemize} + \bigskip \item General structure \begin{itemize} \item Removal of $g_\text{m}$ stage of Gilbert cell $\rightarrow$ more voltage headroom @@ -12,14 +18,6 @@ \item Differential to single-ended conversion $\rightarrow$ dense chip-to-package transition \end{itemize} \bigskip - \item Own simulations - \begin{itemize} - \item Better results to be expected (technology with higher $f_\text{t}$, $f_\text{max}$, stability not considered) - \item Further investigation needed to determine whether unusual LO power behavior is problematic - \item Maybe better results by using current mirrors to set operating points of buffer instead of resistors - \item Maybe better results by replacement of discrete component matching networks by transmission line based ones - \end{itemize} - \bigskip \item Applications of this design \begin{itemize} \item SiGe HBT technology integrable with CMOS $\rightarrow$ scalable, suitable for mixed-signal ICs