From 3f593c47d5979fe5ddc2d3bb9a91e9ee0e1f960d Mon Sep 17 00:00:00 2001 From: Andreas Tsouchlos Date: Sat, 29 Jul 2023 21:52:02 +0200 Subject: [PATCH] Add project files and gitignore --- .gitignore | 32 + CommonSense.kicad_pcb | 2 + CommonSense.kicad_pro | 345 ++++ CommonSense.kicad_sch | 3562 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 3941 insertions(+) create mode 100644 .gitignore create mode 100644 CommonSense.kicad_pcb create mode 100644 CommonSense.kicad_pro create mode 100644 CommonSense.kicad_sch diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..00ceefe --- /dev/null +++ b/.gitignore @@ -0,0 +1,32 @@ +# ---> KiCad +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.kicad_sch-bak +*.kicad_prl +*.sch-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv + +# Backups +*-backups diff --git a/CommonSense.kicad_pcb b/CommonSense.kicad_pcb new file mode 100644 index 0000000..2b8ba10 --- /dev/null +++ b/CommonSense.kicad_pcb @@ -0,0 +1,2 @@ +(kicad_pcb (version 20221018) (generator pcbnew) +) \ No newline at end of file diff --git a/CommonSense.kicad_pro b/CommonSense.kicad_pro new file mode 100644 index 0000000..d133ccc --- /dev/null +++ b/CommonSense.kicad_pro @@ -0,0 +1,345 @@ +{ + "board": { + "3dviewports": [], + "design_settings": { + "defaults": { + "board_outline_line_width": 0.1, + "copper_line_width": 0.2, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "other_line_width": 0.15, + "silk_line_width": 0.15, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.15 + }, + "diff_pair_dimensions": [], + "drc_exclusions": [], + "rules": { + "min_copper_edge_clearance": 0.0, + "solder_mask_clearance": 0.0, + "solder_mask_min_width": 0.0 + }, + "track_widths": [], + "via_dimensions": [] + }, + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, 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